- Posts: 1
- Joined: Thu Jun 20, 2019 6:33 am
- Real Name: Lance Henderson
Thu Jun 20, 2019 6:48 am
We are currently having an issue getting a Duo 2 recognised by our SBC system. We are after some more information about the Duo 2 to understand if there are any settings that we need to change on our SBC side to get the communication working. Currently, the PCIe link is not being recognised at all.
Question we have:
1. How long does the Duo take to enumerate? I.e. do we need to delay enumeration? If so, by how long?
2. Does the Duo support Spread Spectrum Clocking (SSC) or does this need to be disabled?
3. Is the FPGA endpoint using REFCLK from the root controller? Or is it using ts own internal clock as REFCLK
Thanks,
Lance
Question we have:
1. How long does the Duo take to enumerate? I.e. do we need to delay enumeration? If so, by how long?
2. Does the Duo support Spread Spectrum Clocking (SSC) or does this need to be disabled?
3. Is the FPGA endpoint using REFCLK from the root controller? Or is it using ts own internal clock as REFCLK
Thanks,
Lance