The struggle, in processing design.
Posted: Thu Nov 12, 2020 5:03 pmAs some may know, I spent some time on designing an Operating System Architecture and processing instruction set to go with it (refered to as an ISA). Only to have Microsoft put in one hundred man years into one version of windows, and for me to catch an serious illness the present one that is killing me is related to. So, it was pointless to go on. But industry never truely caught up, and all the brain sapping system problems I see all the time, erks me.
What people don't realise, is that processors, in the main, are sloppy and inefficient, as well as system architecture. It's hard to design things very efficiently, as you have to figure out what perfect efficiency is. It is at this point, I loose people with little ability, who presume they know stuff and are superior, and in lack of understanding the obvious, start accusing me of techno babble (truely, as insane as it sounds).
Modern processing us geared towards a legacy of two design trends:. One, classical computer concepts that resulted in the Unix and Linux operating systems, and efficiently doing this and processing compiled C language code, which was the development language of the Unix operating system. Another concept was Reduced Instruction set computing, which relied a bit more on registers to hold bales as they were worked on. The debate between complex and reduced instruction set computing can be viewed a little like this, the Reduce instruction paradigm is a little simpler than a complex one, allowing for better streamlining design and smaller circuited have less physical distance to travel, and can complete cycies faster, and clock faster, or so it seemed. A complex instruction set computer (Cisc the reduced is Risc) can be viewed as allowing any sort of instruction to do any sort of thing. This means that a custom circuits for each job could be used which should beat any group of the reduced RISC instructions , but I'm reality, this might mean a processor the size of a bus, to have a good portion of each needed task on the planet. I tried to figure out a way to beat that custom circuits advantage and succeeded, as a custom circuit that remains powered up was leaking a lot of energy back then, and the extremely small instruction circuited Ives look at, were extremely low energy and tailored to only use as much as the circuited required, dynamically powering down unused parts, which they try to do these days. But I'm reality, complex instruction sets just take up room and become complex to decode. But I'm reality. RISC instruction sets added so many instructions, to bring in more complex tasks to the processors, they have similar numbers of instructions to complex ones, and their sizes have bloated out . However, RISC maintains a bit of an low energy advantage sure to better ISA design principles. The other issue for RISC was that clocks speeds leveled out and required over clocking as part of standard design, but was hampered by energy leakage producing heat, removing advantage of the simpler instruction set to clock faster over Cisc
These are aspects, an intelligent person accesses when designing something, not techno babble.
There is another reality from above, silicon chip circuits are terribly ineffucdbt and slow. Magnetic computing devices are projected to have nearly perfect efficiency at nearly one millionth the energy. Top speed is 2 Thz. I've been trying to figure out how to leverage both those characteristics.
So, on all levels of chip design, there is clear room fur improvement. I've been working towards a minimal instruction set computer based on an more efficient firm or instruction set from mainframe computer days in the 1950/60's. My whole operating system io architecture turned out similar to the vastly superior mainframe and mini computing architectures, which are object like.m, but in a virtual msvhibdy. However, I came to realise a number of other improvements to how things were done, that would allow it to complete with gpu, dsp, fpga, and custom chips. At smaller sizes, with a number of circuited improvements. It is nearly a new way to look at the architecture of the microprocessor and parallel and interprocess communications. The aim is to increase the performance density of chips greatly.
What people don't realise, is that processors, in the main, are sloppy and inefficient, as well as system architecture. It's hard to design things very efficiently, as you have to figure out what perfect efficiency is. It is at this point, I loose people with little ability, who presume they know stuff and are superior, and in lack of understanding the obvious, start accusing me of techno babble (truely, as insane as it sounds).
Modern processing us geared towards a legacy of two design trends:. One, classical computer concepts that resulted in the Unix and Linux operating systems, and efficiently doing this and processing compiled C language code, which was the development language of the Unix operating system. Another concept was Reduced Instruction set computing, which relied a bit more on registers to hold bales as they were worked on. The debate between complex and reduced instruction set computing can be viewed a little like this, the Reduce instruction paradigm is a little simpler than a complex one, allowing for better streamlining design and smaller circuited have less physical distance to travel, and can complete cycies faster, and clock faster, or so it seemed. A complex instruction set computer (Cisc the reduced is Risc) can be viewed as allowing any sort of instruction to do any sort of thing. This means that a custom circuits for each job could be used which should beat any group of the reduced RISC instructions , but I'm reality, this might mean a processor the size of a bus, to have a good portion of each needed task on the planet. I tried to figure out a way to beat that custom circuits advantage and succeeded, as a custom circuit that remains powered up was leaking a lot of energy back then, and the extremely small instruction circuited Ives look at, were extremely low energy and tailored to only use as much as the circuited required, dynamically powering down unused parts, which they try to do these days. But I'm reality, complex instruction sets just take up room and become complex to decode. But I'm reality. RISC instruction sets added so many instructions, to bring in more complex tasks to the processors, they have similar numbers of instructions to complex ones, and their sizes have bloated out . However, RISC maintains a bit of an low energy advantage sure to better ISA design principles. The other issue for RISC was that clocks speeds leveled out and required over clocking as part of standard design, but was hampered by energy leakage producing heat, removing advantage of the simpler instruction set to clock faster over Cisc
These are aspects, an intelligent person accesses when designing something, not techno babble.
There is another reality from above, silicon chip circuits are terribly ineffucdbt and slow. Magnetic computing devices are projected to have nearly perfect efficiency at nearly one millionth the energy. Top speed is 2 Thz. I've been trying to figure out how to leverage both those characteristics.
So, on all levels of chip design, there is clear room fur improvement. I've been working towards a minimal instruction set computer based on an more efficient firm or instruction set from mainframe computer days in the 1950/60's. My whole operating system io architecture turned out similar to the vastly superior mainframe and mini computing architectures, which are object like.m, but in a virtual msvhibdy. However, I came to realise a number of other improvements to how things were done, that would allow it to complete with gpu, dsp, fpga, and custom chips. At smaller sizes, with a number of circuited improvements. It is nearly a new way to look at the architecture of the microprocessor and parallel and interprocess communications. The aim is to increase the performance density of chips greatly.